ABSTRACT - The characteristics of a new low-voltage (2.0 V) logic family (ATL or controlled switching logic) are showed. Its simple realization and performances, both static and dynamic, put it among the best bipolar circuit configurations (TTL-Schottky, I2L, NTL, NTL-CEF, CBL, ECL and its version such as CC-APD-ECL).The application field ranges from discrete to integrated structures (VLSI).

Thanks to a new switching control technique, the implementation of the fundamental logic functions (NAND and NOR) is extremely simple and takes place in modular manner from the NOT gate. The modularity is more marked than the CMOS logic and therefore it allows to reduce the masking operations during the realization procedure.

ATL has been implemented and analysed at the university laboratories of "La Sapienza", Rome (Italy). With 7 US dollars each, five ATL inverter circuits with obselete discrete components on a experimental board have been realised.

In spite of its dimensions (18 mm x 35 mm), the NOT ATL has showed 1.3 ns * 0.60 mW @ 0.8 pJ at 23 C.

Such a discrete logic circuit has never been so fast with the same static power dissipation.

A comparison with the standard logic families (LS, ALS, FAST, HC, AC, VHC, LCX and LVX) under the same conditions has been carried out. Only LVX (SMT) has presented a dynamic DP equal to ATL. However, LVX propagation time is 3.13 ns at 3.3 V.

The time measurements are unload, respecting EIA/JEDEC Standard No.64.

NAND and NOR 2-input ATL have been carried out and they confirm the simulation results. I have simulated the NOT ATL with SPICE models of new discrete components. I have got 543 ps * 78 mW and 635 ps * 6.7 mW with two ATL versions; both have had CLOAD = 15 pF and an input of 10 MHz with tRISE = tFALL = 1 ns.

A remarkable property of ATL is versatility. With few NOT gates, anyone could potentially obtain more than 16 logic functions: NAND, NOR, AND, OR multi-inputs, LATCH RS NAND, LATCH RS NOR, Multiplexers, Trasmission Gates, Buffer 3-state, EX-OR, etc. The high modularity of ATL allows a Gate Array design for any application.

A half-adder ATL takes 750 ps and 1 ns to produce the carry and the sum (CLOAD = 15 pF), respectively (SPICE simulations with discrete components).

ATL has been invented by Andrea Arbore.
ATL has been selected for the prize Focus 2000 dedicated to the best invention conceived in Italy from the first January 1998.
ATL web site has been selected from the Dmoz group and included in the Open Directory Project;
this guarantees correctness and quality of the content [About Open Directory Project].

Web site under construction. Some pages are in Italian, others in English. Sorry.

You can use a web translator like to translate italian pages in your language.

Mirror site: http://studenti.ing.uniroma1.it/~arborean

Published: September 30, 1999

Last Update: February 21, 2002

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