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REFERENCES

TABLE OF CONTENTS

  1. ARTICLES
  2. MONOGRAPHS
  3. APPLICATION NOTES
  4. GUIDES
  5. STANDARDS

Chronological order is respected.

Articles

  1. H. K. Kroemer, "Heterostructure bipolar transistor and integrated circuits," Proc. IEEE, vol. 70, no. 1, pp.13-25, January 1982.
  2. P. M. Solomon, "A comparison of semiconductor devices for high-speed logic," Proc. IEEE, vol. 70, no. 5, pp. 489-509, May 1982.
  3. D. A. Sunderland, "Optimizing n-p-n and p-n-p heterojunction bipolar transistor for speed," IEEE Trans. Electron Devices, vol. ED-34, no. 2, pp. 367-377, February 1987.
  4. P. F. Lu, T. C. Chen, M. J. Saccamango, "Modeling of currents in a vertical p-n-p transistor with extremely shallow emitter," IEEE Electron Device Lett., vol. 10, no. 5, pp. 232-235, May 1989.
  5. T. C. Chen et al., "A submicrometer high-performance bipolar technology," IEEE Electron Device Lett., vol. 10, no. 8, pp. 364-366, August 1989.
  6. S. K. Weidmann et al., "Sub-300-ps CBL circuits," IEEE Electron Device Lett., vol. 10, no. 11, pp. 484-486, November 1989.
  7. G. R. Wilson, "Advances in bipolar VLSI," Proc. IEEE, vol. 78, no. 11, pp.1706-1719, November 1990.
  8. C. T. Chuang, "NTL with complementary emitter-follower driver: a high -speed low-power push-pull logic circuit," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 661-665, April 1991.
  9. P. F. Lu, J. D. Warnock, J. D. Cressler, K. A. Jenkins, K. Y. Toh, "The design and optimization of high-performance, double-poly self-aligned p-n-p technology," IEEE Trans. Electron Devices, vol. 38, no. 6, June 1991.
  10. C. T. Chuang, D. D. Tang, "High-speed low-power AC-coupled complementary push-pull ECL circuit," IEEE J. Solid-State Circuits, vol. 27, no. 4, April 1992.
  11. J. Candelaria et al., "MOSAIC 5 SE: A 6 fJ high-performance bipolar technology," Electronics Lett., vol. 29, no. 20, pp. 1763-1764, September 1993.
  12. J. D. Cressler, J. Warnock, D. L. Harame, J. N. Burghartz, K. A. Jenkins, C. C. Chuang, "A high-speed complementary silicon bipolar technology with 12 fJ power-delay product," IEEE Electron Device Lett., vol. 14, no. 11, pp. 523-526, November 1993.
  13. G. Hill, H. Q. Tserng, T. S. Kim, "65/90 GHz complementary HBT technology," Electronics Lett., vol. 30, no. 7, pp. 597-598, March 1994.
  14. C.T. Chuang, B. Wu, C. J. Anderson, "High-speed low-power cross-coupled active-pull-down ECL circuit," IEEE J. Solid-State Circuits, vol. 30, no. 6, June 1995.
  15. H. C. Tseng, R. C. Hsieh, K. C. Hwang, J. M. Ballingall, " A high- current-gain, high speed P-n-p AlGaAs/InGaAs/GaAs collector-up heterojunction bipolar transistor," Appl. Phys. Lett., no. 67, no. 6, August 1995.
  16. J. Shen, S.Tehrani, H. Goronkin, G. Kramer, R. Tsui, "An Exclusive-Nor based on Resonant Interband Tunneling FET's," IEEE Electron Device Lett., vol. 17, no. 3, pp. 94-96, March 1996.
  17. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, C. Hu, "Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI," IEEE Trans. Electron Devices, vol. 44, no. 3, pp. 414-422, March 1997.
  18. J. Juan- Chico, M. J. Bellido, A. Acosta, A. Barriga, M. Valencia, "CMOS inverter maximum frequency of operation due to digital signal degradation," Electronics Lett., vol. 33, no. 19, pp. 1619-1621, September 1997.
  19. C. Wann et al., "High-performance 0.07-micrometer CMOS with 9.5-ps gate delay and 150 GHz fT," IEEE Electron Device Lett., vol. 18, no. 12, pp. 625-627, December 1997.
  20. T.Onai, E. Ohue, M. Tanabe, K. Washio, "12-ps ECL using low-base resistance Si bipolar transistor by self-aligned Metal/IDP technology," IEEE Trans. Electron Devices, vol. 44, no. 12, pp. 2207-2212, December 1997.
  21. K. K. O, B. W. Scharf, "Effects of buried layer geometry on characteristics of double polysilicon bipolar transistors," IEEE Electron Device Lett., vol. 19, no. 5, pp. 160-162, May 1998.
  22. W. Jin, P. C. H. Chan, M. Chan, "On the power dissipation in Dynamic Threshold Silicon-on-Insulator CMOS inverter," IEEE Trans. Electron Devices, vol. 45, no. 8, pp. 1717-1724, August 1998.

Monographs.

  1. The engineering staff of Texas Instruments Inc., The TTL data book for design engineer, 1973.
  2. E. Taub, D. Schilling, Elettronica integrata digitale, Jackson, 1977.
  3. J. Millman, C. C. Halkias, Microelettronica, Boringhieri, 1978.
  4. V. T. Frolkin, L. N. Popov, Pulse circuits, Mir Publishers, 1982.
  5. I. P. Stepanenko, Fundamentals of microelectronics, Mir Publishers, 1982.
  6. I.T. Agakhanyan, Integrated circuits, Mir Publishers, 1986.
  7. G. Lotti, G. Calcinaro, Tecnologia delle costruzioni elettroniche, vol. I-II-III, La Sovrana, 1987.
  8. J. Millman, A. Grabel, Microelectronics, McGraw-Hill, 1987.
  9. D. A. Hodges, H. G. Jackson, Analisi e progetto di circuiti integrati digitali, Boringhieri, 1988.
  10. R. Giometti, F. Frascari, Elettronica: la logica, Calderini, 1989.
  11. T. Kjellander, Esercitazioni digitali. Misure applicate di tecniche digitali ed impulsive, Philips.
  12. I. Nikolayev, N. Filinyuk, Microelectronic devices and fundamentals of their design, Mir Publishers, 1989.
  13. A. S. Sedra, K. C. Smith, Microelectronic circuits, Saunders College, 1989.
  14. I. Mendolia, U. Torelli, Elettronica digitale e dispositivi logici, Hoepli, 1991.
  15. S. M. Sze, Dispositivi a semiconduttore, Hoepli, 1991.
  16. A. S. Tanenbaum, Architettura del computer, Prentice Hall, 1991.
  17. A.Vladimirescu, Spice, McGraw-Hill, 1995.
  18. G. Ciccarella, A. Londei, F. Loriga, P. Marietti, Sistemi elettronici digitali, Masson, 1996.
  19. T. A. DeMassa, Z. Ciccone, Digital integrated circuits, Wiley, 1996.
  20. G. Moroni, L'oscilloscopio, Jackson, 1997.
  21. P. Van Zant, Microchip fabrication, McGraw-Hill, 1997.
  22. G. Ghione, Dispositivi per la microelettronica, McGraw-Hill, 1998.
  23. P. Spirito, Elettronica digitale, McGraw-Hill, 1998.

 

Application Notes.

Fairchild.
  1. AN. 118, CMOS oscillators, October 1974.
  2. AN. 77, CMOS, the ideal logic family, January 1983.
  3. AN. 363, Designing with TTL, June 1984.
  4. AN. 780, Operating ECL from a single posistive supply, May 1991.
  5. AN. 476, Guide to ALS and AS, March 1995.
  6. AN. 1097, Understanding output drive, March 1998.

 

Harris (Intersil).
  1. AN. MM3046.1, HFA3046/3096/3127/3128 transistor array SPICE models, February 1994.
  2. AN. TB341, Low power technology (LPT) 3.3V logic, December 1996.
  3. AN. TB342, Quiet FCT logic advantages, December 1996.
  4. AN. MM9710, CA3096 and CA3083 transistor array SPICE models, July 1997.

IDT.
  1. AN. 124, 3.3 VOLT logic characteristics and applications, 1995.
  2. AN. 154, Estimating power dissipation in CMOS devices, 1996.

Micron.
  1. TN. 00-06, Bypass capacitor selection for high-speed designs, July 1998.
  2. Article, Micron meets the need for simulation models, 1998.

Motorola.
  1. AN. 1400, MC10/100H640 clock driver family I/O SPICE modelling kit, 1992.
  2. AN. 1401, Using SPICE to analyze the effects of board layout on system skew when designing with the MC10/100H640 family of clock drivers, 1992.
  3. AN. 1403, FACT I/O model kit, 1992.
  4. AN. 1508, High frequency design techniques and guidelines for bipolar gate arrays, 1992.
  5. AN. 1503, ECLinPS I/O SPICE modelling kit, 1996.
  6. AN. 1570, Basic semiconductor thermal measurement, 1996.
  7. MECL Data Book-Section II, Technical data, 1996.
  8. Semiconductor design guide-Section 5, Package and thermal information, 1996.
  9. AN. 1406, Designing with PECL (ECL at +5V), 1998.
  10. DL129-Rev 6, High-speed CMOS logic data.
  11. FAST and LS TTL-Section 1, Selection information FAST/LS TTL.
  12. FAST and LS TTL-Section 2, Circuit characteristics.
  13. FAST and LS TTL-Section 3, Design considerations, testing and applications .
  14. Analog IC device data, Linear and switching voltage regulator: applications information.

National.
  1. AN. 313, DC electrical characteristics of M54HC/MM74HC high speed CMOS logic, June 1983.
  2. AN. 317, AC electrical characteristics of M54HC/MM74HC high speed CMOS logic, June 1983.
  3. AN. 319, Comparison of M54HC/MM74HC to 54LS/74LS, 54S/74S and 54ALS/74ALS logic, June 1983(1995).
  4. AN. 303, HC CMOS power dissipation, February 1984.
  5. AN. 377, DC noise immunity of CMOS logic gates, July 1984.
  6. AN. 376, Logic-system design techniques reduce switching CMOS power, October 1984.
  7. AN. 393, Transmission-line effects influence high-speed CMOS, March 1985.
  8. AN. 610, Terminations for advanced CMOS logic, May 1989.
  9. AN. 661, FAST/FASTr design considerations, March 1990.
  10. AN. 690, Design innovations address advanced CMOS logict noise considerations, June 1990.
  11. AN. 737, Device generated noise measurement techniques, January 1991.
  12. AN. 754, Using logic devices with 25 Ohm series resistors in the outputs, February 1991.
  13. AN. 839, BTL power dissipation calculation, July 1992.
  14. AN. 640, Understanding and minimizing ground bounce, February 1993.
  15. AN. 680, Dynamic threshold for advanced CMOS logic, March 1993.

Philips.
  1. AN. 202, Testing and specifing FAST logic, June 1987.
  2. AN. 212, Package lead inductance considerations in high-speed applications, June 1987.
  3. AN. 241, Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE), June 1992.
  4. AN. 2021, Thermal considerations for FAST logic products, March 1995.
  5. AN. 243, LVT (Low Voltage Technology) and ALVT (Advanced LVT), January 1998.
  6. AN. 246, Transmission lines and terminations with Philips Advanced Logic families, February 1998.
  7. AN. 203, Test fixtures for high speed logic, April 1998.

Siemens.
  1. AN. 024, Parasitic capacitance in bipolar junction transistors, 1997.

Texas Instruments.
  1. AN. SDAA010, Advanced Schottky family, June 1985.
  2. AN. SCBA002, Low-cost, low-power level shifting in mixed-voltage systems, June 1994.
  3. AN. SCA031, EMI prevention in clock-distribution circuits, June 1994.
  4. AN. SCLA008, Using high-speed CMOS and Advanced CMOS logic in systems with multiple Vcc supplies or partial power down, April 1996.
  5. AN. SDYA011, Printed-circuit-board layout for improved electromagnetic compatibility, October 1996.
  6. AN. SDYA014, The Bergeron method, October 1996.
  7. AN. SDYA010, Input and output characteristics of digital integrated circuits, November 1996.
  8. AN. SCEA004, Timing differences of 10-pF versus 50-pF loading, November 1996.
  9. AN. SCBA007A, The bypass capacitor in high-speed environments, November 1996.
  10. AN. SDYA015, Timing measurements with fast logic circuits, November 1996.
  11. AN. SDYA006, Metastable response in 5-V logic circuits, February 1997.
  12. AN. SCBA003C, Next-generation BTL/Futurebus transceivers allow single-sided SMT manufacturing, March 1997.
  13. AN. SCEA003A, GTL/BTL: a low-swing solution for high-speed digital logic, March 1997.
  14. AN. SCBA009C, Thin very small-outline package (TVSOP), March 1997.
  15. AN. SDYA009C, Designing with logic, June 1997.
  16. AN. SCAA035B, CMOS power consumption and Cpd calculation, June 1997.
  17. AN. SCBA004B, Implications of slow or floating CMOS inputs, December 1997.
  18. AN. SCEA005, Migration from 3.3-V to 2.5-V power supplies for logic devices, December 1997.
  19. AN. SCAA034B, Advanced high-speed CMOS (AHC) logic family, January 1998.
  20. AN. SCZA005B, Thermal characteristics of Standard Linear and Logic (SLL) packages and devices, March 1998.
  21. AN. SCEA006A, AVC logic family: technology and applications, August 1998.
  22. AN. SCEA009, Dynamic Output Control (DOC) circuitry: technology and applications, August 1998.

 

Zetex.
  1. AN. 23, Zetex SPICE models, March 1996.

Guides.

  1. Fairchild Semiconductor, Logic selection guide.
  2. Texas Instruments, Device selection guide.
  3. Texas Instruments, AHC/AHCT designer's guide.
  4. Texas Instruments, AVC Advanced Very-low-voltage CMOS logic.
  5. LVL Alliance, Introducing VCX logic.
  6. Motorola, Low voltage CMOS: VCX, LVX, LCX.

 

Standards.

JEDEC.
  1. JESD8-2, Standard for operating voltages and interface levels for low voltage Emitter-Coupled Logic (ECL) integrated circuits, March 1993.
  2. JESD8-3, Gunning Transceiver Logic (GTL) low-level, high-speed interface standard for digital integrated circuits, November 1993
  3. JESD8-A, Interface standard for nominal 3 V/3.3 V supply digital integrated circuits, June 1994.

EIA/JEDEC.
  1. EIA/JESD8-5, 2.5 V ± 0.2 V (normal range), and 1.8 V to 2.7 V (wide range) power supply voltage and interface standard for nonterminated digital integrated circuits, October 1995.
  2. JESD36, Standard for description of low-voltage TTL-compatibile, 5 V-tolerant CMOS logic devices, June 1996.
  3. EIA/JESD8-8, Stub series terminated logic for 3.3 Volts (SSTL_3), August 1996.
  4. JESD59, Bond wire modeling standard, June 1997.
  5. JESD64, Standard for description of 2.5 V CMOS devices with 3.6 V CMOS tolerant inputs and outputs, February 1998.
  6. JESD8-A, Definition of skew specification for standard logic devices, September 1998.

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