Some months ago I made some considerations by myself about the 8 MB limit for the Hardital Big Bang accelerating board. I found it unusual because the maximum addressable amount of RAM is usually a power of 4.
I gave a look at the DRAM controller chip on this board; it is a DP8421A produced by National Semiconductor. I found National's web page listed in the Chip Directory archive. A little research and the data sheets were discovered. Reading a little this sheets was enough to find that my assumption was true. The DP8421 is able to control up to 16 MB of RAM using 1 Mb density chips.
Now I was sure that this expansion could be made, but the question was: how easily ? Today I can answer "quite easily", but I experienced many troubles during its project and realization. Anyway, I did it ! And it's cheap !!
I build this expansion using two 8 MB EDO SIMM; if you choose to use SIMMs, it's mandatory that they are assembled with 1 Mb chips. The data width, instead, is not important. Currently one of my SIMMs uses 16 chips with 1Mbx4 density, the other uses 4 chips with 1Mbx16 density. To check if the SIMM is ok, you have to be sure that the #19 pin is not used (connected to none of the chips on the SIMM).
I had to build a ZIP to SIMM adapter to connect the two SIMMs to the ZIP sockets on the Big Bang. I made the connections using thin wires. Try to keep these wires as short as possible, because they introduce noises and delays, causing wrong reads and writes from/to the memory. In particular the /RAS connections seem to be the most tricky. Only when I soldered these wires directly on the DP8421 socket (instead of the ZIP sockets) I got rid of all the read/write errors. Probably due to this noisy adapter, overclocking the board to 33 Mhz causes the memory read/write errors to reappear. I returned the clock down to 25 Mhz some time ago, as I discovered that my CPU and FPU are 20 MHz devices, already overclocked to 25 MHz by Hardital itself.
The 16 MB RAM does not autoconfig. This is due to the 8 MB autoconfig address space limitation of the Amiga 500/2000. Consequently you must add the memory during the boot using a command like "Addmem". Moreover the 16 MB RAM is formed by 2 separated chunks of 8 MB each. It's also possible that you can't switch to 68000 mode anymore, because there could be some conflict between the two SIMMs, but I haven't tested this (I have no more reasons to degrade my system today).
I use a couple of CMOS gates for this expansion. They introduce a delay in the range of 20-40 ns. I also developed a couple of alternative logic cicuits based on logic gates; they can be faster than my first solution if you build it with TTL chips.
To understand how my hack works you have to know the meaning of some signals.
| Name | Location | Description |
|---|---|---|
| /ML | DP8421 pin # 52; 68030 | When this signal is asserted (low) the DP8421 enters the program mode. It comes from the /RESET signal of the 68030 |
| /RAS0,1,2,3 | DP8421 pin # 38,39,40,41 | These signals are asserted exclusively, i.e. if one is asserted then the other are negated. The asserted one selects its corresponding memory bank. |
| B0,B1 | IC32 pins # 17 and 16; DP8421 pins # 32 and 33 | These signals are generated by the IC32 GAL and sent to the DP8421. When /ML is asserted, their values are used to program the DRAM controller; when /ML is negated, their values are used to generate the /RAS signals. |
To work correctly, the DP8421 must be programmed. The programmation is made reading the status of some signals (B0, B1, ...) as the /ML signal is asserted. Normally the IC32 component (a custom programmed chip) handles the B0 and B1 values both in normal and program mode. When /ML is asserted the correct values are sent to the DP8421 to program it; when /ML is negated the B1 signal is always 0 and only B0 is used to select one of the two memory banks present on the Big Bang.
My idea is simply to use the B1 signal in normal mode too, to be able to address four banks instead of only two.
To allow this I used a couple of electronic switches, called "transmission gates", connected as shown below.
The white lines represent already existing connections, the orange lines are new connection to be made, and the dotted line is a connection which has to be broken.
When /ML is asserted the output of IC32 is sent normally to the DP8421, thus the DRAM controller is correctly programmed. When /ML is negated the A26 address line is connected to the DP8421. When the value of A26 is 0, the usual two memory banks are addressed through /RAS0 and /RAS1; when its value is 1, the new 2 memory banks are addressed through /RAS2 and /RAS3.
If you aren't familiar with the hexadecimal notation, you can read now this little explanation about the translation between hexadecimal and binary numbers.
It's important to configure the two memory chunks with addresses which differ in the bit # 26. As example the usual two memory banks are addressed in the $1200000-$19FFFFF range (0000 0001 xxxx xxxx xxxx xxxx xxxx xxxx); the new two banks, instead, are addressed in the $5200000-$59FFFFF range (0000 0101 xxxx xxxx xxxx xxxx xxxx xxxx). As you can note, the two addresses differ for the value of the A26 bit. E.g., if you execute "addmem 1200000 19FFFFF" and then "addmem 3200000 39FFFFF" (0000 0011 xxxx xxxx xxxx xxxx xxxx xxxx) you will configure the same memory bank twice, because the two addresses have the same value in the A26 bit !!
You can choose to use a different address line, and then configure the memory in different ranges, but remember that the bit # 24 is always 1 when in non-autoconfig mode. The other most significant bits are unused, thus, with my example connection, I can configure the second chunk in the $D200000-D9FFFFF range (0000 1101 xxxx xxxx xxxx xxxx xxxx xxxx).
The things you need to build this expansion are:
First you have to break the existing connection between pin # 16 of IC32 and pin # 33 of the DP8421 DRAM controller. Choose a place where you can see clearly the track and cut it carefully, not too deep in the board.
Next you need to connect the CMOS chips. The connections are shown before and summarized in the next tables.
| 4066 pin # | connected to |
|---|---|
| 1 | not connected |
| 2 | not connected |
| 3 | not connected |
| 4 | not connected |
| 5 | not connected |
| 6 | DP8421 pin # 52 |
| 7 | GND |
| 8 | 68030 A26 |
| 9 | DP8421 pin # 33 |
| 10 | DP8421 pin # 33 (or simply connect it to the previous pin) |
| 11 | IC32 pin # 16 |
| 12 | 4049 pin # 4 |
| 13 | not connected |
| 14 | +5 V |
| 4049 pin # | connected to |
|---|---|
| 1 | +5 V |
| 2 | not connected |
| 3 | not connected |
| 4 | 4066 pin # 12 |
| 5 | DP8421 pin # 52 |
| 6 | not connected |
| 7 | not connected |
| 8 | GND |
| 9 | not connected |
| 10 | not connected |
| 11 | not connected |
| 12 | not connected |
| 13 | not connected |
| 14 | not connected |
| 15 | not connected |
| 16 | not connected |
Finally I built a SIMM to ZIP adapter, but if you own other types of memory chips (ZIP, DIP, 30 pin SIMM, ...) you can project your own adapter. A SIMM to ZIP adapter can be built following the scheme below. Note that many pin of the two SIMM can be connected together, but some has an exclusive connection.
The M1....M16 labels are referred to the ZIP sockets on the Big Bang. The Super Big Bang labels are different !! It seems that the correspondencies are those contained in the next table
| Big Bang ZIP socket label | Super Big Bang ZIP socket label |
|---|---|
| M1 | M1 |
| M2 | M3 |
| M3 | M5 |
| M4 | M7 |
| M5 | M9 |
| M6 | M12 |
| M7 | M13 |
| M8 | M15 |
| M9 | M2 |
| M10 | M4 |
| M11 | M6 |
| M12 | M8 |
| M13 | M10 |
| M14 | M11 |
| M15 | M14 |
| M16 | M16 |
| SIMM pin # | of the SIMM # | connected to |
|---|---|---|
| 1 | both | GND, pin # 5 of any ZIP socket |
| 2 | both | D0, pin # 6 of M1 or M9 ZIP socket |
| 3 | both | D18, pin # 6 of M5 or M13 ZIP socket |
| 4 | both | D1, pin # 7 of M1 or M9 ZIP socket |
| 5 | both | D19, pin # 7 of M5 or M13 ZIP socket |
| 6 | both | D2, pin # 3 of M1 or M9 ZIP socket |
| 7 | both | D20, pin # 3 of M5 or M13 ZIP socket |
| 8 | both | D3, pin # 4 of M1 or M9 ZIP socket |
| 9 | both | D21, pin # 4 of M5 or M13 ZIP socket |
| 10 | both | +5 V, pin # 15 of any ZIP socket |
| 11 | none | not connected |
| 12 | both | A0, pin # 11 of any ZIP socket |
| 13 | both | A1, pin # 12 of any ZIP socket |
| 14 | both | A2, pin # 13 of any ZIP socket |
| 15 | both | A3, pin # 14 of any ZIP socket |
| 16 | both | A4, pin # 16 of any ZIP socket |
| 17 | both | A5, pin # 17 of any ZIP socket |
| 18 | both | A6, pin # 18 of any ZIP socket |
| 19 | none | not connected ! If the SIMM uses this signal, it can't be adapted !! |
| 20 | both | D4, pin # 6 of M2 or M10 ZIP socket |
| 21 | both | D22, pin # 6 of M6 or M14 ZIP socket |
| 22 | both | D5, pin # 7 of M2 or M10 ZIP socket |
| 23 | both | D23, pin # 7 of M6 or M14 ZIP socket |
| 24 | both | D6, pin # 3 of M2 or M10 ZIP socket |
| 25 | both | D24, pin # 3 of M6 or M14 ZIP socket |
| 26 | both | D7, pin # 4 of M2 or M10 ZIP socket |
| 27 | both | D25, pin # 4 of M6 or M14 ZIP socket |
| 28 | both | A7, pin # 19 of any ZIP socket |
| 29 | none | not connected |
| 30 | both | +5 V, pin # 15 of any ZIP socket |
| 31 | both | A8, pin # 20 of any ZIP socket |
| 32 | both | A9, pin # 10 of any ZIP socket |
| 33 | 1 | /RAS1, DP8421 pin # 39 |
| 33 | 2 | /RAS3, DP8421 pin # 41 |
| 34 | 1 | /RAS0, DP8421 pin # 38 |
| 34 | 2 | /RAS2, DP8421 pin # 40 |
| 35 | none | not connected |
| 36 | none | not connected |
| 37 | none | not connected |
| 38 | none | not connected |
| 39 | both | GND, pin # 5 of any ZIP socket |
| 40 | both | /CAS0, pin # 2 of M1, M2, M9 or M10 ZIP socket |
| 41 | both | /CAS2, pin # 2 of M5, M6, M13 or M14 ZIP socket |
| 42 | both | /CAS3, pin # 2 of M7, M8, M15 or M16 ZIP socket |
| 43 | both | /CAS1, pin # 2 of M3, M4, M11 or M12 ZIP socket |
| 44 | 1 | /RAS0, DP8421 pin # 38 |
| 44 | 2 | /RAS2, DP8421 pin # 40 |
| 45 | 1 | /RAS1, DP8421 pin # 39 |
| 45 | 2 | /RAS3, DP8421 pin # 41 |
| 46 | none | not connected |
| 47 | both | /WE,pin # 8 of any ZIP socket, or DP8421 pin # 36 |
| 48 | none | not connected |
| 49 | both | D9, pin # 6 of M3 or M11 ZIP socket |
| 50 | both | D27, pin # 6 of M7 or M15 ZIP socket |
| 51 | both | D10, pin # 7 of M3 or M11 ZIP socket |
| 52 | both | D28, pin # 7 of M7 or M15 ZIP socket |
| 53 | both | D11, pin # 3 of M3 or M11 ZIP socket |
| 54 | both | D29, pin # 3 of M7 or M15 ZIP socket |
| 55 | both | D12, pin # 4 of M3 or M11 ZIP socket |
| 56 | both | D30, pin # 4 of M7 or M15 ZIP socket |
| 57 | both | D13, pin # 6 of M4 or M12 ZIP socket |
| 58 | both | D31, pin # 6 of M8 or M16 ZIP socket |
| 59 | both | +5 V, pin # 15 of any ZIP socket |
| 60 | both | D32, pin # 7 of M8 or M16 ZIP socket |
| 61 | both | D14, pin # 7 of M4 or M12 ZIP socket |
| 62 | both | D33, pin # 3 of M8 or M16 ZIP socket |
| 63 | both | D15, pin # 3 of M4 or M12 ZIP socket |
| 64 | both | D34, pin # 4 of M8 or M16 ZIP socket |
| 65 | both | D16, pin # 4 of M4 or M12 ZIP socket |
| 66 | none | not connected |
| 67 | none | not connected |
| 68 | none | not connected |
| 69 | none | not connected |
| 70 | none | not connected |
| 71 | none | not connected |
| 72 | both | GND, pin # 5 of any ZIP socket |
I also connected a couple of 10 microFarad bypass capacitors between the +5 V and GND inputs near the SIMMs, to avoid a voltage drop during the transitions, but maybe they aren't strictly needed, because there are already bypass capacitors on the SIMMs and near the ZIP sockets.
CHECK EVERYTIME IF THE CONNECTION ARE NOT FAULTY AND THERE ARE NO SHORT CIRCUITS !!!
Now you must set your Big Bang switches and jumpers for 8 MB RAM, non-autoconfig mode as explained on the manual. Then use the "addmem" command (supplied with the board) to configure your memory in the correct addresses ranges.
I try to exstimate the costs (in US dollars) for this hack:
I would like to thank my brother, Andrea "orso", Enrico "lupo", Claudio, Fabio "kurt", Max "gns" and, last but not least, doc. Paolo Canali for their technical support; prof. Paccagnella and prof. Baccolini for their teaches (the things I learned, I applied it to this hack).
Greetings to my company (expecially the girls ;), the Amiga users in Padova and Verona (in Italy, in the world, ...), my home mates, my canadian friend Rino, my family, and everyone who knows me.