Partial Zorro2 slot for the A1200


After releasing my Zorro 2 hack for the A500, I received many requests to develop a similar expansion for the A1200.

The following text is the result of a cooperation between me and Emanuele Minardi (netrage@mediacom.it), one of the first person who ask me for the "porting" to the A1200.

As I already told to some people, the project stops because the 68020 in the A1200 uses a different way (and signals) to transfer data. Only 2 signals are missing for a workng Picasso II adapter !



A1200 intenal slot pinout

pin # signal pin # signal pin # signal
1 reserved 51 D23 101 GND
2 reserved 52 D22 102 +5 V
3 reserved 53 D21 103 FC2
4 reserved 54 D20 104 FC1
5 reserved 55 D19 105 FC0
6 reserved 56 D18 106 /RMC
7 reserved 57 D17 107 reserved
8 reserved 58 D16 108 reserved
9 GND 59 GND 109 reserved
10 +5 V 60 +5 V 110 reserved
11 A23 61 D15 111 /BR
12 A22 62 D14 112 /BG
13 A21 63 D13 113 reserved
14 A20 64 D12 114 /BOSS
15 A19 65 D11 115 /FPUCS
16 A18 66 D10 116 /FPUSENSE
17 A17 67 D9 117 CCKA
18 A16 68 D8 118 /RESET
19 GND 69 GND 119 GND
20 +5 V 70 +5 V 120 +5 V
21 A15 71 D7 121 /NETCS
22 A14 72 D6 122 /SPARECS
23 A13 73 D5 123 /RTCCS
24 A12 74 D4 124 /FLASH
25 A11 75 D3 125 /REG
26 A10 76 D2 126 /CCENA
27 A9 77 D1 127 /WAIT
28 A8 78 D0 128 /KBRESET
29 GND 79 GND 129 /IORD
30 +5 V 80 +5 V 130 /IOWR
31 A7 81 /IPL2 131 /OE
32 A6 82 /IPL1 132 /WE
33 A5 83 /IPL0 133 /OVR
34 A4 84 reserved 134 XRDY
35 A3 85 /RST 135 /ZORRO
36 A2 86 /HLT 136 /WIDE
37 A1 87 reserved 137 /INT2
38 A0 88 reserved 138 /INT6
39 GND 89 SIZE1 139 GND
40 +5 V 90 SIZE0 140 +5 V
41 D31 91 /AS 141 SYSTEM1 (GND)
42 D30 92 /DS 142 SYSTEM0 (GND)
43 D29 93 R/W 143 /xRxD
44 D28 94 /BEER 144 /xTxD
45 D27 95 reserved 145 /CONFIG OUT
46 D26 96 /AVEC 146 AUDIO GND
47 D25 97 /DSACK1 147 AUDIO LEFT
48 D24 98 /DSACK2 148 AUDIO RIGHT
49 GND 99 CPUCLKA 149 +12 V
50 +5 V 100 E Clock 150 -12 V

Signals mapping

Zorro 2 pin # Zorro 2 signal A1200 slot pin # A1200 slot signal Notes
1 GND 9 GND -
2 GND 19 GND -
3 GND 29 GND -
4 GND 39 GND -
5 +5 V 10 +5 V -
6 +5 V 20 +5 V -
7 LOCAL_OWN* ?? - ??? (not used by the Picasso II).This is an output signal to the Buster chip probably used for DMA.
8 -5 V xx - Some power supply (not used by the Picasso II)
9 SLAVEn* ?? - ??? (used by the Picasso II, but I leave it not connected). This is an output signal to the Buster chip probably used for DMA.
10 +12 V 149 +12 V -
11 CONFIG_OUT* - - this signal must go as CONFIG_IN* of the next board (I connected this to pin 12 of my SCSI controller inserted in the expansion port).
12 CONFIG_IN* 145 /CONFIG_OUT this signal must go only to one board (the Picasso) so you must break the connection between the #145 pin of the A1200 internal slot and the #145 pin of the board inserted into it.
13 GND 49 GND -
14 C3* xx - (not used by the Picasso II)
15 CDACB xx - (not used by the Picasso II)
16 C1* xx - (not used by the Picasso II)
17 OVR* 133 /OVR (not used by the Picasso II)
18 XRDY 134 XRDY -
19 INT2* 137 /INT2 (not used by the Picasso II)
20 -12 V 150 -12 V (not used by the Picasso II)
21 BA5 33 A5 -
22 INT6* 138 /INT6 (not used by the Picasso II)
23 BA6 32 A6 -
24 BA4 34 A4 -
25 GND 59 GND -
26 BA3 35 A3 -
27 BA2 36 A2 -
28 BA7 31 A7 -
29 BA1 37 A1 -
30 BA8 28 A8 -
31 BFC0 105 FC0 (not used by the Picasso II)
32 BA9 27 A9 -
33 BFC1 104 FC1 (not used by the Picasso II)
34 BA10 26 A10 -
35 BFC2 103 FC2 (not used by the Picasso II)
36 BA11 25 A11 -
37 GND 69 GND -
38 BA12 24 A12 -
39 BA13 23 A13 -
40 EINT7* 83 /IPL0 (not used by the Picasso II)
41 BA14 22 A14 -
42 EINT5* 82 /IPL1 (not used by the Picasso II)
43 BA15 21 A15 -
44 EINT4* 81 /IPL2 (not used by the Picasso II)
45 BA16 18 A16 -
46 BEER* 94 /BEER -
47 BA17 17 A17 -
48 VPA* xx - (not used by the Picasso II)
49 GND 79 GND -
50 E 100 E (not used by the Picasso II)
51 VMA* xx - (not used by the Picasso II)
52 BA18 16 A18 -
53 RST* 85 /RST (not used by the Picasso II)
54 BA19 15 A19 -
55 HLT* 86 /HLT (not used by the Picasso II)
56 BA20 14 A20 -
57 BA22 12 A22 -
58 BA21 13 A21 -
59 BA23 11 A23 -
60 BRn* 111 /BR (not used by the Picasso II)
61 GND 101 GND -
62 BGACK* xx - (not used by the Picasso II)
63 BD15 61 D15 -
64 BGn* 112 /BG (not used by the Picasso II)
65 BD14 62 D14 -
66 DTACK* xx - (not used by the Picasso II)
67 BD13 63 D13 -
68 READ 93 R/W -
69 BD12 64 D12 -
70 BLDS* - !NOT PRESENT! see next note !
71 BD11 65 D11 -
72 BUDS* - !NOT PRESENT!

Probably on the A1200 (in particular in the 68020) the UDS* and LDS* signals are substituted in some manner by DS* (pin #92). LDS* and UDS* are used by the 68000 to set the size of the data to be transferred: when both are active a word (16 bit) will be transferred, otherwise if only one is active the corresponding upper/lower byte (8 bit) of the word will be transferred.

My hypothesis is that the 68020 uses the SIZE0 and SIZE1 signals to set the size of the data to transfer (and maybe DSACK1 DSACK2 as answer ?), but I'm not sure. Maybe with some logic gates it's possible to "simulate" the behaviour of the LDS* and UDS* signals using those existing on the 68020, but I would need more precise informations.


73 GND 119 GND -
74 BAS* 91 /AS -
75 BD0 78 D0 -
76 BD10 66 D10 -
77 BD1 77 D1 -
78 BD9 67 D9 -
79 BD2 76 D2 -
80 BD8 68 D8 -
81 BD3 75 D3 -
82 BD7 71 D7 -
83 BD4 74 D4 -
84 BD6 72 D6 -
85 GND 139 GND -
86 BD5 73 D5 -
87 GND 139 GND -
88 GND 139 GND -
89 GND 139 GND -
90 GND 139 GND -
91 GND 139 GND -
92 7 MHz xx - (not used by the Picasso II)
93 DOE 131 OE (not used by the Picasso II). I think this signal is a delayed AS* (pin #74). The author of 2000slot used +5 V. I think it is used by DMA boards.
94 BUSRST* 118 /RESET -
95 GBG* 112 /BG (not used by the Picasso II)
96 EINT1* ?? - ??? (not used by the Picasso II)
97 not connected - - not connected
98 not connected - - not connected
99 GND 139 GND -
100 GND 139 GND -

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