; File: ALTIME.ASM [ from ALTIME.BAS ] - Compiled: 23/07/01 15:48:55 ; BAS62 - V 1.1 - Apr 14 1997 ; Registered to: ESTE - S/N: 39073417 ; =================================================================== .TITLE "ALTIME.ASM" .VERS "ST62E60" .PL 60 .LINESIZE 131 .W_ON .ROMSIZE 4 .INPUT "reg.h" ; Symbolic constants _LF .EQU 0Ah _CR .EQU 0Dh _HT .EQU 09h _FF .EQU 0Ch _BS .EQU 08h _SERIN .EQU 01h _KEYB .EQU 02h _USERIN .EQU 04h _SEROUT .EQU 10h _LCDOUT .EQU 30h _USEROUT .EQU 40h IORMASK .EQU 10h ; User variables COPYA .DEF 84h COPYB .DEF 85h COPYC .DEF 86h ZEROM .DEF 87h MAXALT .DEF 88h WORK1 .DEF 89h RETARD .DEF 8Ah NUMERO .DEF 8Bh W1 .DEF 8Ch W2 .DEF 8Dh W3 .DEF 8Eh LECTUR .DEF 8Fh CANAL2 .DEF 90h F .DEF 91h ; System variables _bufDRA .DEF 92h _bufDRB .DEF 93h _bufDRC .DEF 94h .MACRO wdog ldi WDR,_WTCHDOG .ENDM .ORG 80h ; Start User Rom Area _RESET: wdog ldi IOR, IORMASK reti clr _bufDRA clr _bufDRB clr _bufDRC ; User code ; ' ALTIMETRO MISIL CON DIPLAY LED 7 SEG ; .VERS "ST62E60" ; .ROMSIZE 4 ; .input "reg.bas" ; ' Hardware Registers ST62xx ; ' rev 1.0.4 ; Const ; DRA = $c0, ' Port a data register. ; DRB = $c1, ' Port b data register. ; DRC = $c2, ' Port c data register. ; DRD = $c3, ' Port d data register. ; DDRA = $c4, ' Port a direction register. ; DDRB = $c5, ' Port b direction register. ; DDRC = $c6, ' Port c direction register. ; DDRD = $c7, ' Port d direction register. ; IOR = $c8, ' Interrupt option register. ; DWR = $c9, ' Data rom window register. ; ORA = $cc, ' Port a option register. ; ORB = $cd, ' Port b option register. ; ORC = $ce, ' Port c option register. ; ORD = $cf, ' Port d option register. ; ADR = $d0, ' A/D data register. ; ADCR = $d1, ' A/D control register. ; PSC = $d2, ' Timer prescaler register. ; TCR = $d3, ' Timer counter register. ; TSCR = $d4, ' Timer status control register. ; ARMC = $d5, ' AR-Timer Mode Control register ; ARSC0 = $d6, ' AR-Timer Status Control register 0 ; ARSC1 = $d7, ' AR-Timer Status Control Register 1 ; WDR = $d8, ' Watchdog register. ; DWDR = $d8, ' alias per Digital Watchdog register ; ARLR = $db, ' AR-Timer Load register ; ARRC = $d9, ' AR-Timer Reload / Capture register ; ARCP = $da, ' AR-Timer Compare register 1 ; OSCR = $dc, ' Oscillator Control Register ; SPIMISC = $dd, ' SPI Miscellaneous register ; SPIDSR = $e0, ' SPI Data/Shift register ; SPIDIV = $e1, ' SPI Divide register ; SPIMOD = $e2, ' SPI Mod Control Register ; DRBR = $e8, ' Data Ram/EEPROM Bank Register ; EECTL = $ea, ' EEPROM Control Register ; TMZ = $07, ; DOUT = $04, ; GEN = $10, ' Enable all interrupts. ; ESB = $20, ' Edge Selection Bit (IRQ1) ; LES = $40, ' Level/Edge Selection Bit (IRQ2) ; IORMASK = $10, ' ENABLE mask ( 'ENABLE' loads this value into IOR ) ; LF = $0A, ' Useful constants ; CR = $0D ; ; poke DDRA, %00000001 ' ldi 0C4h, 01h ; poke ORA, %00001001 ldi 0CCh, 09h ; poke DRA, %00001000 ldi 0C0h, 08h ; poke DDRB, %11001111 ' ldi 0C5h, 0CFh ; poke ORB, %11001111 ldi 0CDh, 0CFh ; poke DRB, %00000000 ldi 0C1h, 00h ; poke DDRC, %00011100 ' ldi 0C6h, 1Ch ; poke ORC, %00011100 ldi 0CEh, 1Ch ; poke DRC, %00000000 ldi 0C2h, 00h ; copya=%00001001 ldi COPYA, 09h ; copyb=%10000001 ldi COPYB, 81h ; copyc=%00000000 ldi COPYC, 00h ; poke dra,copya ld A, COPYA ld 0C0h, A ; poke drb,copyb ld A, COPYB ld 0C1h, A ; poke drc,copyc ld A, COPYC ld 0C2h, A ; DELAY 1000 ldi X, 01h ldi V, 0FFh call _lldelay dec X jrnz $-06h ldi V, 8Fh call _lldelay ldi V, 55h wdog dec V jrnz $-04h ; GOSUB LECAD wdog call LECAD ; DELAY 1000 ldi X, 01h ldi V, 0FFh call _lldelay dec X jrnz $-06h ldi V, 8Fh call _lldelay ldi V, 55h wdog dec V jrnz $-04h ; GOSUB LECAD wdog call LECAD ; ZEROM=CANAL2 ld A, CANAL2 ld ZEROM, A ; MAXALT=0 ldi MAXALT, 00h ; pipo: PIPO: wdog ; GOSUB LECAD wdog call LECAD ; WORK1=ZEROM-CANAL2 ld A, ZEROM sub A, CANAL2 ld WORK1, A ; IF CANAL2>ZEROM THEN ld A, CANAL2 cp A, ZEROM jrnc $+03h jp _IF000 jrnz $+03h jp _IF000 ; WORK1=0 ldi WORK1, 00h ; ENDIF _IF000: ; IF WORK1>MAXALT THEN ld A, WORK1 cp A, MAXALT jrnc $+03h jp _IF001 jrnz $+03h jp _IF001 ; MAXALT=WORK1 ld A, WORK1 ld MAXALT, A ; ENDIF _IF001: ; WORK1=MAXALT ld A, MAXALT ld WORK1, A ; GOSUB BINBCD wdog call BINBCD ; for retard=1 to 5 ldi RETARD, 01h _FOR002: ; Compare with 05h ld A, RETARD cpi A, 05h jrc $+04h jrz $+03h jp _FOR003 ; gosub plex wdog call PLEX ; next retard inc RETARD wdog jp _FOR002 _FOR003: ; goto pipo jp PIPO ; ; ' ------------------ MULTIPLEX 2 DIGITOS ----------- ; plex: PLEX: wdog ; ; numero=W1 ld A, W1 ld NUMERO, A ; set 0,addr(copya) set 00h, 84h ; res 7,addr(copyb) res 07h, 85h ; gosub conver7 wdog call CONVER7 ; poke dra,copya ld A, COPYA ld 0C0h, A ; poke drb,copyb ld A, COPYB ld 0C1h, A ; poke drc,copyc ld A, COPYC ld 0C2h, A ; delay 10 ldi V, 03h call _lldelay ldi V, 97h wdog dec V jrnz $-04h ; res 0,addr(copya) res 00h, 84h ; set 7,addr(copyb) set 07h, 85h ; numero=W2 ld A, W2 ld NUMERO, A ; gosub conver7 wdog call CONVER7 ; poke dra,copya ld A, COPYA ld 0C0h, A ; poke drb,copyb ld A, COPYB ld 0C1h, A ; poke drc,copyc ld A, COPYC ld 0C2h, A ; delay 10 ldi V, 03h call _lldelay ldi V, 97h wdog dec V jrnz $-04h ; ; return wdog ret ; '----------------------- BCD A 7 SEG ----------------------- ; conver7: CONVER7: wdog ; if numero=0 then ld A, NUMERO cpi A, 00h jrz $+03h jp _IF004 ; res 1,addr(copyb) res 01h, 85h ; res 2,addr(copyb) res 02h, 85h ; set 3,addr(copyb) set 03h, 85h ; res 6,addr(copyb) res 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; res 3,addr(copyc) res 03h, 86h ; res 4,addr(copyc) res 04h, 86h ; endif _IF004: ; if numero=1 then ld A, NUMERO cpi A, 01h jrz $+03h jp _IF005 ; set 1,addr(copyb) set 01h, 85h ; set 2,addr(copyb) set 02h, 85h ; set 3,addr(copyb) set 03h, 85h ; set 6,addr(copyb) set 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; res 3,addr(copyc) res 03h, 86h ; set 4,addr(copyc) set 04h, 86h ; endif _IF005: ; if numero=2 then ld A, NUMERO cpi A, 02h jrz $+03h jp _IF006 ; res 1,addr(copyb) res 01h, 85h ; res 2,addr(copyb) res 02h, 85h ; res 3,addr(copyb) res 03h, 85h ; set 6,addr(copyb) set 06h, 85h ; set 2,addr(copyc) set 02h, 86h ; res 3,addr(copyc) res 03h, 86h ; res 4,addr(copyc) res 04h, 86h ; endif _IF006: ; if numero=3 then ld A, NUMERO cpi A, 03h jrz $+03h jp _IF007 ; res 1,addr(copyb) res 01h, 85h ; set 2,addr(copyb) set 02h, 85h ; res 3,addr(copyb) res 03h, 85h ; set 6,addr(copyb) set 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; res 3,addr(copyc) res 03h, 86h ; res 4,addr(copyc) res 04h, 86h ; endif _IF007: ; if numero=4 then ld A, NUMERO cpi A, 04h jrz $+03h jp _IF008 ; set 1,addr(copyb) set 01h, 85h ; set 2,addr(copyb) set 02h, 85h ; res 3,addr(copyb) res 03h, 85h ; res 6,addr(copyb) res 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; res 3,addr(copyc) res 03h, 86h ; set 4,addr(copyc) set 04h, 86h ; endif _IF008: ; if numero=5 then ld A, NUMERO cpi A, 05h jrz $+03h jp _IF009 ; res 1,addr(copyb) res 01h, 85h ; set 2,addr(copyb) set 02h, 85h ; res 3,addr(copyb) res 03h, 85h ; res 6,addr(copyb) res 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; set 3,addr(copyc) set 03h, 86h ; res 4,addr(copyc) res 04h, 86h ; endif _IF009: ; if numero=6 then ld A, NUMERO cpi A, 06h jrz $+03h jp _IF010 ; res 1,addr(copyb) res 01h, 85h ; res 2,addr(copyb) res 02h, 85h ; res 3,addr(copyb) res 03h, 85h ; res 6,addr(copyb) res 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; set 3,addr(copyc) set 03h, 86h ; res 4,addr(copyc) res 04h, 86h ; endif _IF010: ; if numero=7 then ld A, NUMERO cpi A, 07h jrz $+03h jp _IF011 ; set 1,addr(copyb) set 01h, 85h ; set 2,addr(copyb) set 02h, 85h ; set 3,addr(copyb) set 03h, 85h ; set 6,addr(copyb) set 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; res 3,addr(copyc) res 03h, 86h ; res 4,addr(copyc) res 04h, 86h ; endif _IF011: ; if numero=8 then ld A, NUMERO cpi A, 08h jrz $+03h jp _IF012 ; res 1,addr(copyb) res 01h, 85h ; res 2,addr(copyb) res 02h, 85h ; res 3,addr(copyb) res 03h, 85h ; res 6,addr(copyb) res 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; res 3,addr(copyc) res 03h, 86h ; res 4,addr(copyc) res 04h, 86h ; endif _IF012: ; if numero=9 then ld A, NUMERO cpi A, 09h jrz $+03h jp _IF013 ; set 1,addr(copyb) set 01h, 85h ; set 2,addr(copyb) set 02h, 85h ; res 3,addr(copyb) res 03h, 85h ; res 6,addr(copyb) res 06h, 85h ; res 2,addr(copyc) res 02h, 86h ; res 3,addr(copyc) res 03h, 86h ; res 4,addr(copyc) res 04h, 86h ; endif _IF013: ; ; return wdog ret ; '------------------------ binario a bcd ------------------ ; binbcd: BINBCD: wdog ; W1=0 ldi W1, 00h ; W2=0 ldi W2, 00h ; W3=0 ldi W3, 00h ; asm { LD A,WORK1 LD W1,A LDI W2,0 LDI W3,0 BCD1 LD A,W1 CPI A,10 JRC FBCD SUBI A,10 INC W2 LD W1,A LD A,W2 CPI A,10 JRZ SBCD JP BCD1 FBCD RET SBCD LDI W2,0 INC W3 JP BCD1 ; } ; return wdog ret ; '--------------- rutina lectura convertidor analogico ------------- ; 'el resultado retorna en CANAL2 ; 'realizo 255 medidas para la media (19 ms xtal= 8mhz) ; LECAD: LECAD: wdog ; LECTUR = 0 ldi LECTUR, 00h ; CANAL2 = 0 ldi CANAL2, 00h ; F = 0 ldi F, 00h ; asm{ ldi LECTUR,0 ldi CANAL2,0 ldi F,255 LECAD1 ldi ADCR,30h ;comienzo convercion LOOP1 jrr 6,ADCR,LOOP1 ;espera eoc ld a,ADR ;carga convercion en a ldi WDR,0feh ;recarga registro wd add a,LECTUR jrnc LECAD2 inc CANAL2 LECAD2 ld LECTUR,a dec F jrz LECAD4 jp LECAD1 LECAD4 ld a,LECTUR cpi a,128 jrc LECAD3 inc CANAL2 LECAD3 ret ;media es la media de 225 lecturas ; } ; RETURN wdog ret ; '------------------------------------------------------------------ ; 'restore data1 ; 'rdvar: ; ' reg_a = i ; ' asm{ ; ' dec a ; makes Basic index 0 based ; ' addi a, DATA1.D ; ' ld _DATAPTR, a ; ' } ; ' read a ; ' ; ' next ; 'return ; 'data1: data $01,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,$00 ; Stop execution at blocking fence. _endprog: jp _RESET ; ============= ; LIBRARIES ; ============= ;=============================================================== ; _lldelay ; ; INPUT : V (external cycles) ; OUTPUT : nothing ; NEEDS : ; Manages wdog; ; min delay: 1546 cycles i.e. 2.512ms @ 8Mhz ; max delay: 395266 cycles i.e. 642.4ms @ 8Mhz ; Cycles: (14 + 255*6)*V + 2 cycles; ;=============================================================== _lldelay wdog ldi W,0FFh ;================================================================ ; needs 255*6 = 1530 cycles, 2.487ms ;================================================================ _lldely1 dec W jrnz _lldely1 ;================================================================ dec V jrnz _lldelay ret ; === end _lldelay ; ====================== ; INTERRUPT VECTOR TABLE ; ====================== .ORG 0FF0h _adc_irq: nop ; IRQ #4, A/D reti _tim_irq: nop ; IRQ #3, TIMER reti irq2_irq: nop ; IRQ #2 reti irq1_irq: nop ; IRQ #1 reti .ORG 0FFCh _nmi_irq: nop ; IRQ #0, NMI reti _res_irq: jp _RESET ; User Reset Vector. .END