FLS 24Cxxx i2c e2prom programmer sw

Summary:

Description
Supported devices
Hardware requirements
Performances
Tech details
Tested devices
Download
Contacts

Description:

24Cxxx is an i2c eeprom programmer software for Linux OS capable to Read / Write / Verify the 24CXX/24CXXX family.

24Cxxx is distribuited under the GPL version 2.

Supported devices:

`24Cxxx supported e2prom types`
`24C01`	`24C04`	`24C16`	`24C64`	`24C256`
`24C02`	`24C08`	`24C32`	`24C128`	`24C512`

Hardware requirements:

24Cxxx needs a very low cost serial interface type Ludipipo or JDM plus a little socket adapter that you can build, even if you hold the iron like an hammer :), in no more than 15 min (see the Hardware file in the distribution).

Performances:

Here are reported some indicative performances of the programmer with a 24C16 target on two different machines :

`24Cxxx Indicative performaces`
`Operation`	`Athlon 650`	`486DX5 133`
`read`	`0.72 s`	`1.45 s`
`safe write`	`1.21 s`	`5.64 s`
`optimized` `write cycle time`	`0.55 s`	`1.61 s`

Tech details:

Peak performances are achieved using :

Sequential read, using the internal data word address counter register of the IC

Page write; the page size optimized per device

and scheduling the program in soft real time mode

Note that the default programming speed is the safest possible (10ms WCT that is the maximum characterized on datasheets) and that even the low-end devices can work down to 2ms and beyond (I was able to repetitive program a couple of 24C02 with WCT @1.2ms and a 24C16 @0.7ms w/o ACK problems) so setting WCT @2ms should be a good compromise between speed and relaiability.

To change the WCT settings simply add "-s delay_in_us" to the command line; obviously setting this too low will raise an "ACK ERROR !" indicating the exceed of the device operative limits.

The picture below represents the bus timings relative to the the athlon machine:

[Bus timing picture on Athlon 650]

The maximum measured clock rate is 144KHz so I think that you cannot reach the 400KHz limit (for operations @5V) even on the fastest overclocked machines, but is still possible to go beyond the limits of the various setup & hold times; in that case you can find the hack to decrease the bit rate in the README file (please let me know if this happens).

A final consideration about timings; due to the fact that the program is running in user mode (with the scheduling algorithm set to RT_FIFO and priority to max) I found that the accuracy on the athlon workstation is (w/ load < 1%) ~10us between 100us and 2ms then decay to 10ms; in other words setting a delay of 3ms will produce a WCT of 10ms.

This is still acceptable, in fact we can fine tune the WCT for the hi-end devices and leave the default for the smallest ones, where the time spent for programming is really low.

Tested devices:

`Device`	`min` `WCT`	`Contributor`
`AMTEL(TM) 24C02`	`1.2ms`	`Author`
`AMTEL(TM)` `24C04`	`1.0ms`	`Author`
`AMTEL(TM)` `24C16`	`0.7ms`	`Author`

Your contributions are welcome

Download:

24Cxxx-1.0.tar.gz (23K) source distribution.

Contacts:

If you modify the program, find a bug, have suggestions, success reports or simply find this program useful please let me know sending an e-mail to the following address not forgetting to include "24Cxxx" in the subject:

Author : Luca Ferretti
E-mail : luca.ferretti@wind.it

These pages are (C)FLS Luca Ferretti Systems and last revised on Sep 23 2000